
/*
包含一些宏

PLL晶振处理

    `PLL_DEF 放在moudle top 里

    `PLL_RV_DEF 放在 alta_rv32 里面, 如
        alta_rv32 rv32(
            `PLL_RV_DEF
        )

    定义后，sys_gck 为全局时钟

*/

`define PLL_RV_DEF                                  \
		.sys_clk(sys_clk),                          \
        .sys_ctrl_pllEnable(PLL_EN),                \
        .sys_ctrl_pllReady(PLL_LOCK),               \
        .sys_ctrl_clkSource(sys_ctrl_clkSource),    \
        .sys_ctrl_stop(sys_ctrl_stop),              \
        .sys_ctrl_sleep(sys_ctrl_sleep), \
        .sys_ctrl_standby(sys_ctrl_standby), \
        .resetn_out(sys_resetn),

`define PLL_DEF(_FREQ,_CLKFB_LOW,_CLKFB_HIGH) \
wire[4:0] PLL_CLKOUT; \
defparam pll_inst.CLKIN_FREQ      = _FREQ;  \
defparam pll_inst.CLKFB_HIGH      = _CLKFB_LOW;  \
defparam pll_inst.CLKFB_LOW       = _CLKFB_HIGH;  \
defparam pll_inst.CLKIN_HIGH      = 8'd0;   \
defparam pll_inst.CLKIN_LOW       = 8'd1;   \
defparam pll_inst.CLKIN_TRIM      = 1'b1;   \
defparam pll_inst.CLKIN_BYPASS    = 1'b0;   \
defparam pll_inst.CLKFB_TRIM      = 1'b1;   \
defparam pll_inst.CLKFB_BYPASS    = 1'b0;   \
defparam pll_inst.CLKDIV0_EN      = 1'b1;   \
defparam pll_inst.CLKDIV1_EN      = 1'b1;   \
defparam pll_inst.CLKDIV2_EN      = 1'b1;   \
defparam pll_inst.CLKDIV3_EN      = 1'b0;   \
defparam pll_inst.CLKDIV4_EN      = 1'b0;   \
defparam pll_inst.CLKDIV4_EN      = 1'b0;   \
defparam pll_inst.CLKOUT0_HIGH    = 8'd0;   \
defparam pll_inst.CLKOUT0_LOW     = 8'd1;   \
defparam pll_inst.CLKOUT0_TRIM    = 1'b1;   \
defparam pll_inst.CLKOUT0_BYPASS  = 1'b0;   \
defparam pll_inst.CLKOUT0_DEL     = 8'd0;   \
defparam pll_inst.CLKOUT0_PHASE   = 3'd0;   \
defparam pll_inst.CLKOUT1_HIGH    = 8'd0;   \
defparam pll_inst.CLKOUT1_LOW     = 8'd4;   \
defparam pll_inst.CLKOUT1_TRIM    = 1'b1;   \
defparam pll_inst.CLKOUT1_BYPASS  = 1'b0;   \
defparam pll_inst.CLKOUT1_DEL     = 8'd0;   \
defparam pll_inst.CLKOUT1_PHASE   = 3'd0;   \
defparam pll_inst.CLKOUT2_HIGH    = 8'd255; \
defparam pll_inst.CLKOUT2_LOW     = 8'd255; \
defparam pll_inst.CLKOUT2_TRIM    = 1'b0;   \
defparam pll_inst.CLKOUT2_BYPASS  = 1'b0;   \
defparam pll_inst.CLKOUT2_DEL     = 8'd0;   \
defparam pll_inst.CLKOUT2_PHASE   = 3'd0;   \
defparam pll_inst.CLKOUT3_HIGH    = 8'd255; \
defparam pll_inst.CLKOUT3_LOW     = 8'd255; \
defparam pll_inst.CLKOUT3_TRIM    = 1'b0;   \
defparam pll_inst.CLKOUT3_BYPASS  = 1'b0;   \
defparam pll_inst.CLKOUT3_DEL     = 8'd0;   \
defparam pll_inst.CLKOUT3_PHASE   = 3'd0;   \
defparam pll_inst.CLKOUT4_HIGH    = 8'd255; \
defparam pll_inst.CLKOUT4_LOW     = 8'd255; \
defparam pll_inst.CLKOUT4_TRIM    = 1'b0;   \
defparam pll_inst.CLKOUT4_BYPASS  = 1'b0;   \
defparam pll_inst.CLKOUT4_DEL     = 8'd0;   \
defparam pll_inst.CLKOUT4_PHASE   = 3'd0;   \
defparam pll_inst.FEEDBACK_MODE   = 3'b100; \
defparam pll_inst.FBDELAY_VAL     = 3'b100; \
defparam pll_inst.VCO_POST_DIV    = 1'b1;   \
alta_pllve pll_inst (                       \
.clkin(PIN_HSE),                            \
.pfden(1'b1),                               \
.resetn(PLL_EN),                            \
.phasecounterselect(3'b0),                  \
.phaseupdown(1'b0),                         \
.phasestep(1'b0),                           \
.scanclk(1'b0),                             \
.scanclkena(1'b0),                          \
.scandata(1'b0),                            \
.configupdate(1'b0),                        \
.clkfb(pll_clkfb),                          \
.clkfbout(pll_clkfb),                       \
.clkout0(PLL_CLKOUT[0]),                    \
.clkout1(PLL_CLKOUT[1]),                    \
.clkout2(PLL_CLKOUT[2]),                    \
.clkout3(PLL_CLKOUT[3]),                    \
.clkout4(PLL_CLKOUT[4]),                    \
.lock   (PLL_LOCK));                        \
alta_gclksw gclksw_inst (                   \
.resetn(sys_resetn),                        \
.ena   (!sys_ctrl_stop),                    \
.clkin0(PIN_HSI),                           \
.clkin1(PIN_HSE),                           \
.clkin2(PLL_CLKOUT[0]),                     \
.clkin3(),                                  \
.select(sys_ctrl_clkSource),                \
.clkout(sys_clk));                          \
wire sys_gck;                               \
assign bus_clk = sys_gck;                   \
(* keep *) alta_gclkgen gclksw_gen (        \
.clkin (sys_clk),                           \
.ena   (!sys_ctrl_stop),                    \
.clkout(sys_gck0));                         \
/* Location: CLKCTRL_G5 FIXED_COORD */      \
(* keep *) alta_io_gclk gclksw_gclk (       \
    .inclk (sys_gck0),                      \
    .outclk(sys_gck));